Low Power MOS Circuit Design and Testing @ Koneru Lakshmaiah Education Foundation, Guntur

Participants Information

Participants:	45
Speakers:	06
Female participants:	07
Male participants:	38
Participants from SC/ST category:	04
Research Scholars:	None

Lab Sessions

• Hands on from Coreel

Topics Covered

• Overview of low power VLSI design
• Data converter strategies under lowpower
• Testing strategies
• Low power CMOS Circuits
• Low power architectures
• Low power design strategies at sysytem level
• Statistical variations aware modelling and optimization of CMOS and FinFET circuits
• PMIC

List of Speakers

Mr. M. Venkata Krishna Reddy, Design Engineer, Texas Instruments, Bangalore

Dr. Srihari Rao. P, Associate Professor, NIT Warangal

Dr. P. Muralidhar, Associate Professor, NIT Warangal

Mr. Nagendra bandi, Design Engineer, CoreEL Technologies, Hyderabad

Mr. K. Krishna Mahesh, Design Engineer, Texas Instruments, Hyderabad

Dr. Zia Abbas, Assistant Professor, IIIT Hyderabad

Feedback Summary

Good resource persons and Effective lecture sessions.

Excellent program and its conduct.

The basic fundamental concepts taught by every resource person was very effective.

Good accommodation and hospitality.

Suggestions from Participants

Required more hands on sessions.

Applications with respect to signal processing can be added in the program.