Recent Advancements in XILINX and ASIC Designs @ JNTUA College of Engineering(Autonomous), Anantapuramu

Participants Information

Participants:	58
Speakers:	07
Female participants:	21
Male participants:	32
Participants from SC/ST category:	22

Lab Sessions

• Vivado Design FLow Simulation
• Hardware Debugging Working
• IP Integrator Implementing
• Creating Own IP Peripheral
• Vivado HLS FLow Creating Processor System
• Full custom Design Flow
• Basic concepts in DRC
• Additional Feature of nmDRC
• Introduction to LVS, Process Flow Debugging
• Introduction to PEX, xRC and XL Flows
• Introduction to PERC, Design Flows
• Design for Test Concepts

Topics Covered

• Implementation of 8 bit adder on Xilinx
• Implementation of 8 bit multiplier using adaptive hold logic on Spartan3E
• Introduction & Recent Trends in Xilinx FPGA's 7 Series Architecture Overview
• Vivado Design Flow Synthesis, Implementation Tescniaques and Static Timing Analysis
• VHDL Programming
• ML/DL Resources
• ASIC Design Methodologies
• VLSI Chip Design – Industry Perspective
• VLSI DSP Architecture

List of Speakers

Dr. J. Ravi Kumar, Assistant Professor, NIT Warangal

Mr. Nagendra Bandi, Application Engineer, CoreEL Technologies Pvt Ltd, Hyderabad

Mr. Rajesh Murugan, Application Engineer, CoreEL Technologies Pvt Ltd, Hyderabad

Dr. P. Muralidhar, Associate Professor, NIT Warangal

Dr. S. Aruna Mastani, Assistant Professor, J.N.T.U.A.C.E. Ananthapuramu

Dr. Y. Narasimha Murthy, Lecturer, SSBN Degree & PG College

Sri K. V. Sridhar, Associate Professor, NIT Warangal

Feedback Summary

Participants gained knowledge on most of the recent tools used in VLSI Design.

FDP was very effective and motivative to improve the teaching and research skills of the participants.

Hands on sessions were very useful to the participants.

FDP was well organized.

Suggestions from Participants

More time should be alloted for Lab sessions.