Trends in SoC Design and Its Applications @ Vasavi College Of Engineering (Autonomous), Hyderabad

Participants Information

Participants:	40
Speakers:	07
Female participants:	20
Male participants:	20
Participants from SC/ST category:	06
Research Scholars:	07

Lab Sessions

• Hands-on Building Digital filters with MATLAB for golden reference
• Hands-on Design of HDL code generation compatible filters in Simulink
• Hands-on Design of real-time audio filter
• Hands-on Design of real-time audio filter and Deployment on ZedBoard

Topics Covered

• Lecture on SOC Architectures
• HW/SW Co-Design on SOC String Matching
• ZYNQ-SOC Architecture
• Creating Project with IP Cores and Implementing on Hardware
• Adding Custom IP Core to the project and Implementing on Hardware
• IP Integrator Design Flow ( Targeting only processor in ZYNQ)
• Creating Custom IP Core using IP Integrator
• Model-Based design for HW/SW Co-Design for SOC
• Low power VLSI Architectures/ SOC Power Management
• Interfacing PS and PL via AXI bus in Simulink
• Trends in SoC Design and Challenges

List of Speakers

Prof. Amit Acharya, Associate Professor, IIT Hyderabad

Dr. P. Muralidhar, Associate Professor, NIT Warangal

Prof. Pawankumar Fakatkar, Mathworks, Pune

Mr. Anil Terker, Scientist –G, Anurag, DRDO, Hyderabad

Prof. N. S. Murthy, Professor, Hyderabad

G. Venkateswarlu, Senior Research Scholar, IIT Hyderabad

Sri. B. Nagendra & Team -CoreEl, SoC Design Lab, Bangalore

Feedback Summary

The concepts were explained with clarity.

Excellent hands on sessions.

It was good combination of lecture sessions and hands on.

All the sessions were good enough to motivate towards the research work.

Suggestions from Participants

Required more hands on sessions.