VLSI Design Verification and Testing @ Lendi Institute of Engineering & Technology, Vizianagaram

Participants Information

Participants:	44
Speakers:	07
Female participants:	12
Male participants:	32
Participants from SC/ST category:	08
Research Scholars:	None

Lab Sessions

• Hands on Coreel
• Coreel Technologies - Mentographics front end verification tool
• Circuit level verification hands on coreel
• Handson simulators Techfluent sol

Topics Covered

• Digital IC Design
• Hardware Description Languages - Data types, Concurrent Statements
• Architectures
• System level design and verification
• Hardware Verification through Simulation Mentor graphics tool Coreel
• Inticacies of design verification at circuit level
• Great code editor autocomplete Syntax validation and quick fixes Techfluent sol
• Hierarchy Vie Integraters with Linters Code formatting options Net search Techfluent sol
• Advanced Type Time Linting Compilation denedencies State machine Techfluent sol
• Industry standards on testing and verification
• State of the art tools and methods for VLSI design verification
• Implementation of Discrete time signal processing integrated circuits and verification

List of Speakers

Dr. B. Lakshmi, Associate Professor, NIT Waranagal

Mr. B. Nagendra, Sr. Application Er, CoreEL Technologies Pvt. Ltd.

Dr. B. Anand, Associate Professor, IIt Roorkee

N. Bala Dastagiri, Engineer, Techfluent Pvt. Ltd.

G. Sudha Kiran, Engineer, Techfluent Pvt. Ltd.

M. V. Krishnareddy, Analog Design Manager, Texas Instruments

Dr. P. Sreehari Rao, Associate Professor, NIT Waranagal

Feedback Summary

Effective presentation by Expertized and well experienced resource persons.

Good insight into the new tools.

Excellent program and good course schedule.

Effective hands on session using software tools.

Suggestions from Participants

Require more hands on sessions.

Architecture should be included in the program along with VLSI Design & Verification.