VLSI Chip Design Hands on using open source EDA (NKN Summer Course) @ E & ICT Academy, NIT Warangal

Participants Information

Participants:	36
Speakers:	06
Female participants:	09
Male participants:	27
Participants from SC/ST category:	08
Research Scholars:	09

Lab Sessions

• Interactive Hands-on Session 1 - (To study the importance of standard cell library and design & characterize one cell using MAGIC Layout tool and ngSPICE for SPICE simulations)
• Interactive Hands-on Session 2 - (To study various components of RISC-V microprocessor based SoC and review all components using MAGIC Layout tool)
• Interactive Hands-on Session 3 - (To do pre-layout timing analysis of SoC using OpenSTA, chip planning using MAGIC and block-level placement/routing using qflow RTL2GDS opensource EDA toolchain)
• Interactive Hands-on Session 4 - (To do hierarchical placement/routing using pads and blocks, and perform sign-off checks viz. LVS/DRC using Magic)
• Interactive Hands-on Session 5 - (To perform post-layout timing analysis using OpenSTA and engineering change order (ECO) using Tritonsizer)

Topics Covered

• Module 01 - SoC Planning
• Module 02 - Floor planning & timing analysis
• Module 03 - Placement, Clock tree synthesis
• Module 04 - Global routing and Detailed routing
• Module 05 - Analog and Mixed Signal Circuit, Specifications to Design, Layout & GDS

List of Speakers

Dr. Anand Bulusu, Associate Professor, IIT Roorkee

Mr. Kunal P Ghosh, Director, VSD Corp. Pvt. Ltd.

Dr. Imon Mondal, Assistant Professor, IIT Kanpur

Dr. Suhakumar Reddy, IIT Hyderabad

Dr. H. S. Jatana, Group Head - Design and Process group, SCL, Dept of Space Mohali

Mr. Uday Khambate, Scientist/Engineer, SCL Chandigarh

Feedback Summary

The concepts were explained with clarity.

Questions and discussions were encouraged.

Allotted number of classes were held and evaluation was done regularly.

Text/Reference materials were appropriate for the course.

Suggestions from Participants

Required more hands on sessions.